Protean

Protean is a general-purpose protocol emulator for the Jane Street protocol emulator ASIC competition, built on the Tiny Tapeout IHP shuttle. Four hardware contexts run transport-triggered programs from an on-chip SRAM. They take turns on one shared datapath in fixed time slots, so each context has its own timing and the design has one trace in cycle order. A host loads programs and data over SPI or QSPI.

Status

The specification is reviewed. Development has started with the ISA file and the tools. TODO.md holds the work order and the schedule.

Architecture at a glance

• IHP SG13G2, 130 nm, CMOS5L, 6x4 tiles, 50 MHz core clock.
• Four contexts in a fixed-slot barrel. Each runs at up to 12.5 MHz, or 25 MHz with two slots.
• 512 instruction words in an IHP SRAM macro, enough to keep every protocol resident.
• 32-bit instructions. Each is one guarded transport from a source port to a destination port, with a side-set and a delay.
• Guards that skip or wait. ALU ports with immediates. A zero-overhead repeat.
• Per context: PC, four 16-bit registers, 32-bit OSR and ISR, 4-word TX and RX FIFOs, a fractional divider.
• Pin writes aligned at period boundaries, so contexts started together run in lockstep.
• TX and RX line coders for CAN and USB, with their own divider. Two 16-bit CRC contexts.
• FIFO chaining for bridges, a timestamp for sniffing, pin-pair loopback for self-test.
• The TPSM SPI and QSPI host bus.

Protocols

UART, SPI master and slave, I2C, PS/2, JTAG, SWD, CAN 2.0 with arbitration and ACK, USB Low-Speed packets, 1-Wire, WS2812, a pin sniffer, and bridges. docs/protocols.md has the programs.

Documents

Document	Contents
PLAN.md	Goal, settled decisions, rules, risks
TODO.md	Work order, schedule, cut list
AGENTS.md	Rules for working in this repository
docs/review.md	Review of the earlier designs
docs/requirements.md	Requirements
docs/decisions.md	Decision log
docs/arch.md	Hardware specification
docs/isa.md	Instruction set
docs/host.md	Host interface and configuration map
docs/protocols.md	Protocol programs
docs/verification.md	Verification plan
docs/tooling.md	Tools and build
docs/tempo.md	The timed language

Lineage

Protean follows TPSM, a two-slot TTA, and Tessera, a PIO-style multi-machine design. It keeps TPSM's transports, line coder, host bus, and verification flow, and Tessera's independent program counters. docs/review.md explains why.

License

Licensed under the Apache License, Version 2.0.

Copyright 2026 Dragos Bajanica.